1. Field of the Invention
This invention relates to control of system memory and more particularly to maintaining system memory in a self refresh state during a power savings state in which power is removed from the memory controller.
2. Description of the Related Art
In order to save power during various power savings states in personal computer systems, it is common to shut down power being supplied to substantial portions of some or all of the integrated circuits in the computer system. Various power management and configuration mechanisms are defined by the Advanced Configuration and Power Interface (ACPI) specification, Revision 1.0b, dated Feb. 2, 1999, which is incorporated herein by reference.
The ACPI specification defines global system operating states G0, G1, G2 and G3. G0 is a working state, G1 is a sleeping state, G2 is a soft off state and G3 is a mechanical off state. In the G1 sleeping state, the computer consumes a small amount of power, and the system appears to be off to the user, e.g., the display is off. However, the system can be restarted without rebooting the operating system (OS) because a sufficient portion of the system context has been saved. Within the G1 sleeping state, the ACPI specification defines a number of sleep states S1–S3. The S1 state is a low wake-up latency state in which system context is not lost. A low wake-up latency means that the system returns to normal operation from the sleep state within a short time, e.g., less than 1 second. The S2 sleep is also a low wake-up latency state, however, CPU and cache context is lost and thus needs to be restored during the resume operation. In the S3 state, the system memory remains powered up and system context, e.g., the contents of processor registers and other system devices, are stored in system memory. The S3 state is also referred to as the suspend-to-RAM state. The wake-up latency from the S3 state is on the order of 3–5 seconds. The S4 state (suspend to disk) is the lowest power and longest latency state in which system context is stored in non volatile storage such as the system hard disk. Wake-up latency can be on the order of 8 or more seconds.
Referring to FIG. 1, an exemplary prior art computer system 100 is shown, which includes CPU 101, north bridge 102, south bridge 103 and system memory 104. The north bridge connects to CPU 101 via host bus 105. The north bridge provides a bridge function between the host bus and peripheral component interconnect (PCI) bus 107. The north bridge also provides the memory control function for system memory 104. Other parts of the computer system include a graphics card 109 and various PCI devices 111.
When the system enters the S3 sleep state, the entire CPU 101 and portions of north bridge 102 are shut down. However, at least a portion of north bridge 102 needs to be kept powered up to keep system memory in self refresh mode. Specifically, during the S3 state, system memory needs to be kept in self refresh mode to avoid system context being lost (since it is dynamic random access memory (DRAM)). Thus, at least the portion of the north bridge interfacing with the system memory 104 has to be maintained powered up in the S3 state to ensure system memory remains in self refresh mode.
In one prior art approach, illustrated in FIG. 1, north bridge 102 is divided into a plurality of different power planes, which each power plane providing voltage for a specific function. For example, a separate 3.3 V power plane 112 is provided for the Accelerated Graphics Port (AGP) interface, a 1.6 V power plane 114 is provided to interface to host bus 105, a 3.3 V power plane 116 provides power to PCI bus 107 interface, a 2.5 V power plane 118 provides power to interface to system memory 104 and a separate 2.5V core logic power plane 120 provides power for the core logic of north bridge 102.
During a power savings mode, typically the core logic power plane 120 is powered down along with those power planes not needed to control logic that remains powered up during the particular sleep state. However, 2.5 V power plane 118 needs to be maintained powered up to keep memory control signals at appropriate levels to ensure the DRAM in system memory 104 is refreshed during the sleep state.
Because certain printed circuit boards (PCBs), especially those used in desktop computers are limited to four wiring layers, it can be difficult to partition the power plane to support all of the power rails to the north bridge in a manner that follows good design practice. Accordingly, one solution is to provide a single 2.5 V power rail for both the core and the system memory interface. However, that limits the amount of power savings that can be achieved since a large portion of north bridge 102 has to remain powered up during suspend to RAM state to maintain system memory 104 in self refresh state. That can increase the S3 state power consumption.
An additional factor to be considered is that integrated circuits having multiple power planes have added design and test complexity. For example, the interfaces between the power planes require additional logic to ensure that signals coming from power planes that are powered down and going to power planes that are powered up, are forced to a known state when entering the power plane that is powered up. Also, signals being provided from logic that is powered into logic that is not powered, should be driven low.
It would be desirable to have a power savings approach that can maximize the amount of power that can be saved during sleep states without resulting in additional power planes. Further, it would be desirable to limit the number of power planes on a chip to minimize the additional logic required for signals crossing power plane boundaries.